Method for preparing electronic circuit units



July 9, 1968 I MOORE 3,391,451

METHOD FOR PREPARING ELECTRONIC CIRCUIT UNITS Filed Mafch 22, 1966 2 Sheets-Sheet 1 a 46 52 56 VACUUM 44 SOURCE & common. ULTRASONIC HAR MONIC 54 WELDER SUPPRESSOR )(Y VACUUM MICROMANIPULATOR PUMP INVENTOR ROBERT P. MOORE ATTORNEY July 9, 1968 P MOORE 3,391,451

METHOD FOR PREPARING ELECTRONIC CIRCUIT UNITS Filed March 22, 1966 2 Sheets-Sheet z FEQB 2 Fm. FEG, 4b 12 26 2o 22 2s 12 WW Am United States Patent ,0 "ice 3,391,451 METHOD FOR PREPARING ELECTRONIC CIRCUIT UNITS Robert P. Moore, Warminster, Pa, assignor to Sperry Rand Corporation, New York, N.Y., a corporation of Delaware Filed Mar. 22, 1965, Ser. No. 441,611 11 Claims. (Cl. 29-577) ABSTRACT OF THE DISCLOSURE A planar glass substrate having metallic conductors evaporated thereon is provided. The conductors include raised pedestal portions for receiving an integrated circuit chip. The chip has conductive pads which are visually aligned with the pedestal portions by viewing the substrate from below. After chip alignment, ultrasonic energy is applied to the chip to effect a weld between the chip and the substrate.

This invention relates to electronic circuit units, and methods and apparatus for preparing electronic circuit units. In particular, this invention relates to a method, an apparatus and an article wherein an integrated circuit chip is directly affixed to a circuit substrate.

In the past, integrated circuit chips (also termed monolithic or hybrid circuits) have been prepared wherein such a chip usually includes a plurality of active elements such as transistors, resistors, capacitors and the like, intercoupled in an integral manner on a single silicon chip. Each chip was packaged individually in a packaging container known as a can or flat-pack. Individual leads are connected to the packaged chip for connection to exterior circuitry. However, the cost of packaging containers, such as cans or flat-packs, is relatively expensive, and the cost of utilizing such packaged chips requiring lead connections is high.

Thus, it becomes an object of this invention to utilize an integrated circuit chip without the need for utilizing a special package such as a can or flat-pack.

It is another object of this invention to provide, as a novel article of manufacture, a substrate having an electronic circuit adherently affixed thereon with an integrated circuit chip directly connected thereto.

It is still another object of this invention to provide a novel electronic circuit unit including an integrated circuit chip directly connected thereto wherein the integrated circuit chip can be replaced without destroying said circuit unit.

It is yet another object of this invention to provide for a novel method for connecting an integrated circuit chip unit with a substrate.

Still another object of this invention is to provide for novel apparatus for connecting an integrated circuit chip to an electronic circuit contained on a substrate.

In accordance with one embodiment of this invention, a planar glass substrate has metallic conductors evaporated thereon, the conductors including raised pedestal portions for receiving an integrated circuit chip. The integrated circuit chip contains pads or lands for contacting and mating with the conductors. The integrated circuit chip is placed on top of the pedestal portions of the evaporated wires and ultrasonically welded thereto. Thus, as a final article of manufacture, integrated circuit chips are directly connected to the evaporated wires. The integrated circuit chips are welded to the wires with limited ultrasonic energy so that, upon detection of failure of a chip, the failed chip is twisted thereupon removing the failed chip from the substrate without resulting damage to the substrate whereupon a replacement chip can be subsequently welded thereupon.

Patented July 9, 1968 In accordance with another embodiment of this invention, novel apparatus is provided including a support for holding a circuit substrate wherein the support has an aperture therein for viewing the substrate from the bottom. The substrate is held down by suitable means such as vacuum applied by a vacuum pump. An integrated circuit chip is traversed from a tray to the upper surface of the substrate by means of a holder to which vacuum is applied by a suitable source. A welding unit, relatively free of harmonic distortion, is utilized for welding the integrated circuit chip to the metallic pedestals on the substrate. Optical alignment is provided by viewing the integrated circuit chip through the substrate through the aperture of the support.

Other objects and advantages of this invention, together with its construction and mode of operation, will become more apparent from the following description when read in conjunction with the accompanying drawing in which like reference symbols refer to like components and parts and in which various elements are illustrated in an exaggerated magnified state and in which:

FIG. 1 is a diagrammatic elevated view of apparatus in connection with one embodiment of this invention;

FIG. 1a is a perspective view of a portion of FIG. 1, illustrating a portion of the holder and welding tip shown in FIG. 1;

FIG. 2 is a top view of a substrate including evaporated wires and pedestals;

FIGS. 3a, 3b, and 30 form a set of cross sectional views illustrating a method for preparing metallic conductors and pedestals upon a suitable substrate;

FIGS. 4a and 445 form a set of views illustrating another method for preparing evaporated wires and pedestals upon a suitable substrate;

FIG. 5a is a set of views showing one type of welding tip for use in practicing one embodiment of this invention;

FIG. 5b is a set of views showing another type of welding tip for use in practicing another embodiment of this invention; and

FIG. 6 is a bottom view (partly in broken section) of a substrate and integrated circuit chips attached thereupon to said substrate, as viewed through the aperture of the support illustrated in FIG. 1.

Referring to FIG. 1, there is shown a transparent planar substrate 10, such as glass, having one surface 12 thereof placed in an upright position, While the other surface 14 rests upon a support 16, having an aperture 18 therein. A plurality of metallic conductors 20 including raised pedestal portions 22 at terminal portions thereof are deposited upon the surface 12 of the substrate 10. Referring to FIGS. 3a, 3b, and 30 there is shown various steps of one method for preparing metallic conductors together with pedestals. As illustrated in FIG. 3a, a film 24 of evaporated aluminum from A to 1 mil in thickness is deposited on the surface 12 of the glass substrate 10. The film 24 is subsequently etched by means of known photo etching and masking techniques, well known in the art, to provide raised etched pedestals 26, as shown in FIG. 3b.

Following the preparation of the pedestals 26, the surface 12 of the substrate 10 is masked and aluminum conductors are evaporated through the mask onto the surface 12 of the substrate 10 covering the pedestals 26. The conductors are evaporated from 5,000 to 50,000 angstroms, preferably 20,000 angstroms, in thickness, thereby providing aluminum conductors 20 having pedestal portions 22 over the original etched pedestals 26, as illustrated in FIG. 30.

Another embodiment of the invention is illustrated in FIGS. 4a and 4b which set forth a different set of steps for preparing the substrate. The substrate 10 is masked by a mask containing the desired locations of the pedestals, and metallic pedestals are initially and directly evaporated through the mask to a thickness in the range from A to 1 mil in thickness, thereby providing for pedestals 26 on top of the surface 12 of the subtrate as shown in FIG. 4a. Subsequent to the deposition of the evaporated pedestals 26 as shown in FIG. 4a, a different mask is place\; upon the surface 12 for the location of the conductors and metallic aluminum interconnecting leads are evaporated through the mask to a thickness in the range as described hereinabove, preferably 20,000 angstroms, thereby providing for an interconnected set of leads 20, including pedestal portions 22.

By way of example, and not by limitation, the dimensions of the substrate 10 are 1" x 2" x an integrated circuit is, generally, approximately 40 mils square.

Referring to FIGS. 1 and In, there is shown an integrated circuit chip 28. A plurality of circuit chips 28 are located on a tray 38 which acts as a storage location for said chips 28. Numerous chips are, usually, placed upon a single substrate 19. Initially, the substrate 10 is placed with its bottom surface 14 on top of the support 16 so that a chip 28 can be placed directly onto the surface 12 of the substrate 10, above the aperture 1.8 within the support 16. Suitable apertures within the support 16 are utilized for coupling orifices 32 via a hose 34 to a vacuum pump 36 which is controlled by suitable means (not shown). The support 16 is movable to and fro in the horizontal directions by a suitable manipulation means shown in FIG. 1 as an XY micromanipulator 38. A chip holder 40, traversable about a pivot 4-2, has suction applied through an orifice 44 therein by means of a suitable vacuum source control means 46, which may be a vacuum source common or similar to the vacuum pump 36.

The holder 40 is initially traversed about the pivot 42 to the tray to vacuum pick up a chip 28, via suction applied to the orifice 44; the holder is then rotated about the pivot 42, and lowered by a suitable means such as a cam 48 to lower the chip 28 on top of the desired pedestals 22 of the substrate 10.

The positioning of the integrated circuit chip 28 with regard to the pedestals 22 of the conductors 29 is best achieved by viewing with the eye 51 through a suitable lens system 53 and suitable mirror 55 through the aperture 18 of the support 16 and through the surface 14 through the substrate 1.6 is thereby view the pedestal portions 22 of the conductors 20 with respect to the corresponding pads or lands 62 of the integrated circuit chip 28 (FIG. 6). Upon suitable manipulation of the XY micromanipulator 38, suitable alignment is achieved.

Upon placing the chip 28 on top of the pedestals 22 of the conductors 20, welding then proceeds.

Ultrasonic energy at an operating frequency, for example, 60.5 kc., is applied relatively free of harmonic distortion to the integrated circuit chip 28 by a suitable means 50, which, in the embodiment shown in FIG. 1, includes an ultrasonic Welder 52 which is coupled to a welding instrument 54 through a suspension system 56 which acts as a harmonic suppressor. Primarily, fundamental energy is thereby provided from the ultrasonic welder 52 through the harmonic suppressor 56 to the welding instrument 54 directly to the integrated circuit chip 28. Energy is provided by the welding instrument 54 to the center of the chip 28 so that the chip 28 is simultaneously welded to all of the pedestals 22 therein below, the energy being transmitted through the chip to each pedestal 22 and land 62 being substantially uniform.

The Welding instrument 54 has two types of tips in the preferred mode as practiced by the applicant.

Referring to FIG. 5a, there is shown a welding instrument 54 having a tapered tip 58. The tip 58 is tapered at an angle of 45 and has a pointed tip which is rounded to a 3 mils radius. The diameter of the instrument, preferably, is 0.062".

in another embodiment the welding tip 54, as illustrated in FIG. 512, has a diameter of 0.062" and has a tapered tip 58 of 45 with a recessed point 69 which is recessed to a 9 mil radius. Both the pointed tip and the recessed tip have proven satisfactory. Either tip produces reliable bonding and each has the advantage of self alignment and use with integrated circuit chips regardless of size or shape.

By way of example, and not by limitation, ultrasonic energy was supplied from a welder having a selected out put power from 0 to 20 watts (variable through a frequency range of 59.2 to 61.8 k.c.), and a variable pulse duration of from 0 to 1.5 seconds.

Reliable bonds are made with a great degree of variance in power, bonding time and bonding force applied to the tip. These variables are optimized for and dictated by the type of bond required; that is, permanent or replaceable. A permanent type bond is easily achieved with a 3 pound bonding force wherein deliberate removal of a welded chip damages the glass substrate. In other cases, a weaker but reliable bond where, upon removal of the chip, the pedestals are still capable of being bondedis achieved. In this latter example, a force of 1 pound is considered optimum for bonding to allow replacement of the chip.

Integrated circuit chip pad location, and a number of pads are determined by the circuit design. A 10 pad chi can be satisfactorily bonded to a substrate by practicing the teachings of this invention.

In one practical embodiment of this invention a commercial micromanipulator and a commercial ultrasonic unit were used. The manipulator was used in conjunction with the optic system for precise control of work. The ultrasonic unit in conjunction with either bonding tip as described above, with harmonic energy suppressed, supplies the energy to the tip to produce the bonding.

Only suflicient bonding force (preferably 1 pound) is used to adhere the chip to the pedestals. Excessive force (such as 3 pounds) permanently adheres the chip to the pedestal whereby removal of the chip by twisting causes damage to the substrate. By providing a small force of 1 pound during welding, the chip can be afiixed to the board or support 10, whereby, when desired to remove a faulty chip, the chip can be twisted and simply removed without damage to the pedestals 22 whereupon a replacement chip can be welded upon the undamaged pedestals.

Flexibility of bonding parameters provides precise control for permanent irreplaceable type bond. No heat is required.

The method described herein eliminates wire bonding methods used in the prior art to attach integrated circuitry to associated packaging. Bonding techniques used in the past required individual pad bonding with flying wires. Wire bonding required a minimum of two bonds to connect a single pad, in the past. In contrast, in practicing the invention described hereinabove fewer bonds are necessary, and all connections on a multiple pad chip are made simultaneously in a minimum of time.

Although the preferred embodiments have been described, other variations will become apparent to those ordinarily skilled in the art without departing from the spirit and scope of this invention. Thus, transparent substrates other than glass may be used, such as plastic; other metals or compounds other than aluminum can be used. Dimensions are illustrative and are not meant to limit the invention, it being understood that it is desired that the invention he limited solely by the scope of the allowed claims.

The embodiments of the invention in which an exclu- SlVe property or privilege is claimed are defiend as follows:

1. The method of producing an electronic circuit unit comprising:

(a) providing a transparent substrate;

(b) evaporating a metallic coating on said substrate;

(c) photo-etching pedestal portions on said coating;

(d) evaporating metallic conductors onto said substrate and said pedestals;

(e) providing an integrated circuit chip having conductive portions thereon corresponding in location for mating with said pedestal portions;

(f) positioning said circuit chip on said substrate with the conducting portions in alignment with said pedestal portions;

(g) visually observing the foregoing alignment operation from below the substrate; and

(h) welding said integrated circuit chip to said substrate, whereby said conductive portions are juxtaposed with and adherent to said pedestal portions.

2. The method as claimed in claim 1 wherein each chip has ultrasonic energy applied thereto to effect the welding thereof to said substrate.

3. The method as claimed in claim 2 wherein said chip has ultrasonic energy at a fundamental frequency centrally applied thereto.

4. The method as claimed in claim 3 wherein said ultrasonic energy is applied to said chip with a pointed tip.

5. The method of producing an electronic circuit unit comprising:

(a) providing a transparent glass substrate;

(b) evaporating a metallic circuit pattern on said substrate including metallic pedestals on portions of said pattern;

(c) providing an integrated circuit chip having conductive portions corresponding in location for mating with said circuit pattern at said metallic pedestals;

(d) placing said integrated circuit chip over said metallic pedestals in juxtaposed mated relation therewith;

(e) providing an ultrasonic welding system including (1) ultrasonic generating means for providing a signal at a fundamental frequency,

(2) a harmonic suppression suspension system coupled to said generating means for suppressing harmonic therefrom, and

(3) a welding instrument having a tapered tip;

and

(f) applying said tapered tip to the center of said chip for applying energy at only said fundamental frequency thereto for welding said chip to said substrate.

6. The method of producing an electronic circuit unit comprising:

(a) providing a transparent substrate;

(b) evaporating a relatively thick metallic coating through a mask to form a plurality of pedestals on said substrate;

(c) evaporating a relatively thin metallic coating through a second mask to form a plurality of metallic conductors, said pedestals being formed contiguous with said conductors;

(d) placing an integrated circuit chip having conductive portions corresponding to said pedestals over said pedestals;

(e) aligning the conductive portions on said chip with the pedestals on said substrate;

(f) visually observing the foregoing alignment from below the substrate; and

(g) applying ultrasonic energy, reasonably free of harmonic distortion, with a tapered tip to the center of said chip, said tapered tip being one selected from the group including:

(1) a pointed tip, and

(2) a recessed tip.

7. The method of producing an electronic circuit unit comprising:

(a) providing a transparent substrate having a metallic circuit pattern having a plurality of metallic pedestals thereon;

(b) providing an integrated circuit chip having a plurality of conductive portions corresponding to said pedestals for mating therewith;

(c) aligning said integrated circuit chip onto said pedestals in juxtaposed mated relation therewith;

(d) visually observing the foregoing alignment from below the substrate; and

(e) welding the chip to the substrate by applying ultrasonic energy, reasonably free of harmonic distortion, onto the central portion of said integrated circuit chip with a tapered tip.

8. The method as claimed in claim 7 wherein said energy is only sufficient to form a weak bond between said chip and said substrate.

9. In the art of affixing an integrated circuit chip having conductive portions on one side thereof to the metallic raised pedestals of a circuit pattern affixed to one side of a transparent substrate, the method of affixing said chip to said substrate including (a) placing one side of said chip in proximate relation with said one side of said substrate wherein said conductive portions correspond in location for mating with said pedestals;

(b) optically aligning said chip with said substrate by viewing said chip, and its associated conductive portions through the other side of said substrate; and

(c) upon optical alignment of said chip with said pedestals, welding said chip to said pedestals on said substrate.

10. The method of producing an electronic circuit unit comprising:

(1) providing a transparent substrate;

(2) placing a metallic circuit ptttern on said substrate including raised metallic pedestal portions thereon;

(3) placing said substrate containing said pattern onto a movable support having an aperture therein, said pattern being placed face up;

(4) providing means for holding said substrate;

(5) providing an integrated circuit chip having conductive portions thereon corresponding to said pedestals portions for mating therewith;

(6) optically aligning said chip with said substrate by viewing said chip, and its associated conductive portions, through said aperture and through said substrate, and moving said substrate and said chip in alignment with each other; and

(7) applying ultrasonic harmonic-free energy to the central portion of said integrated circuit chip, at the side opposite to said conductive portions, with a tapered tip, said tip being tapered at an angle with its cross-section lying within the range 35 to 55.

11. The method as claimed in claim 10 wherein said energy is only sufficient to form a weak bond between said integrated circuit chip and said circuit pattern on said substrate, whereby said chip can be removed from said circuit pattern by a twisting motion without damaging said substrate.

References Cited UNITED STATES PATENTS 2,937,358 5/1960 Bulger 29-1555 2,966,429 12/ 1960 Darrel 29-1555 3,028,814 2/1962 Bodine 29-470 X 3,169,892 2/1965 Lemelson 29-1555 3,199,002 8/ 1965 Martin 317-234 3,255,511 6/ 1966 Weissenstern 29-15 5.5 3,271,625 9/1966 Caracciolo 317-101 3,292,240 12/ 1966 McNutt 29-1555 WILLIAM I. BROOKS, Primary Examiner. 

